This invention relates to a programmable logic device (PLD) or field programmable gate array (FPGA). In particular, it relates to the implementation of a structure for routing signals within the device.
A programmable logic device is an integrated circuit, which includes a large number of logic elements, usually arranged in the form of an array.
After manufacture, these logic elements can be combined, by programming the possible interconnections between the logical elements in a particular way, so that the device performs a particular desired set of functions.
In order to allow the required interconnections to be made, the programmable logic device includes a routing structure. The routing structure may, for example, allow very efficient communication between logic elements which are positioned very close to one another within the device, while also allowing communication between elements which are separated by greater distances. The requirement for efficient communication between logic elements is balanced against the consideration that providing the routing structure uses resources in the device which could otherwise be used for other purposes.
After manufacture of the programmable logic device, functions are then allocated to the logic elements, in such a way that logic elements, which will need to communicate with each other on a regular basis in order to perform those functions, are positioned appropriately, with respect to the routing structure.
When the intended functionality of the device requires that a bus structure be provided, this can be achieved by appropriate programming of the logic elements in the programmable logic device. However, large numbers of the available logic elements may be required to implement the desired bus structure in some cases.